This invention relates generally to integrated circuits, and more specifically, to testing the functionality of integrated circuits.
Integrated circuits are frequently referred to as being a xe2x80x9csystem on a chipxe2x80x9d. Such devices are manufactured and designed to contain embedded core data processor wherein the embedded core communicates with peripherals, memory, or other circuitry on the same substrate. The embedded core may be designed and/or provided by a first group of individuals who license the embedded core to a second group of individuals who complete the system on a chip with their design arranged to interface with the embedded core. Therefore, testing of integrated circuits is made increasingly difficult due to differing design and test methodologies.
The embedded core, which is only a portion of the total integrated circuit, typically contains a plurality of input and output terminals. If the embedded core is kept as a separate structure during test pattern generation and is not bundled together with the rest of the integrated circuit logic for test pattern generation, then there is an access problem related to the plurality of input and output terminals of the embedded core. In most cases, there is no direct access to the embedded core for providing test vectors or for other test purposes.
One of the primary challenges in test and design-for-test (DFT) is the reduction of total test cost. There are many attributes to the test cost including the cost of tester equipment, test time and the space overhead associated with making an integrated circuit testable. As the number of transistors on an integrated circuit increases, so does the number of test vectors that are required to test the integrated circuit. An increase in test vector volume therefore increases test time as well as the requirement on test equipment memories. Together these factors negatively impact the cost of test. As designs increase in complexity, the impact for non-functional logic (i.e. logic dedicated for test purposes) remains high and undesirable. In addition to these problems, additional challenges include increased test power. When testing integrated circuits, circuits typically generate much more power than ever generated during a normal operational mode.
One solution that has been adapted in the industry to address some of the above problems is the use of Logic Built-In-Self-Test (LBIST) that is the ability of a circuit to test itself. The idea behind LBIST is to have both a pattern generator and a response analyzer on the integrated circuit. The use of a pattern generator reduces the volume of required external test vectors that reduces required tester memory. In addition, LBIST circuitry can remove problems associated with test accessibility, especially with embedded cores.
There are several different test architectures that support LBIST. One architecture is known as Self-Testing Using MISR and Parallel PRPG (Pseudo-Random Pattern Generator), or STUMPS. This architecture applies predetermined pseudo-random data through scan chains as test data to implement various tests. MISR is an acronym for Multiple Input Signature Register and is a Linear Feedback Shift Register (LFSR) configured as a signature analyzer that allows multiple data input ports to provide test data to be observed and compressed. There are commercially available software tools that support the STUMPS architecture. Attributes of the STUMPS architecture include centralized and separate BIST architecture, multiple scan paths and no boundary scan. A STUMPS architecture is only capable of testing (observing a response from) a circuit under test once per each scan load/unload. Most test architectures can only test either per scan load/unload or per clock and not both. For the STUMPS architecture, once a test polynomial for either the PRPG or MISR is chosen, it is fixed throughout the test. Unfortunately, a fixed polynomial leaves the circuit under test with many random-pattern-resistant faults requiring special care for handling.
Another test architecture is known as the BILBO (Built-In Logic Block Observer) architecture. The BILBO architecture is a xe2x80x9ctest per clockxe2x80x9d architecture. That is, a new test pattern is applied and results observed on every clock. This architecture is characterized by test registers in a specific configuration that are inserted into the circuit structure at appropriate places. Predetermined pseudo-random test information is presented to the circuit under test and clocked through the circuitry to determine if an expected result is provided. The test determines whether the circuitry receiving the test information is functional. A BILBO xe2x80x9ctest per clockxe2x80x9d scheme often requires a higher hardware overhead than the STUMPS xe2x80x9ctest per scanxe2x80x9d scheme.
Embedded semiconductor cores also utilize a test access mechanism or xe2x80x9cwrapperxe2x80x9d to provide control and observation access to a core in isolation of other circuits. A wrapper can be a conventional multiplexer or a plurality of storage elements that surround the core and through which inputs to the core and outputs from the core pass for test purposes. During normal functional operation (or normal mode of operation), the wrapper allows signals to cross from the customer-specified logic into the core unaltered, and similarly allows data to pass from the core to the customer-specific logic unaltered. Additionally, a test mode is provided whereby scanned sequential elements (the plurality of speed path test cells that create the xe2x80x98wrapperxe2x80x99) provide controllability points for core inputs that are capable of launching transitions into core inputs for speed path testing at-speed. In addition, the plurality of speed path test cells in the wrapper also provides storage for capturing and observing embedded core outputs when an output of the embedded core is speed path tested.
Known uses of BIST, whether in the BILBO architecture or in the STUMPS architecture, are not optimal for integrated circuits due to associated test costs. Cost issues associated with test arise whether the pin count of integrated circuits is large or small.